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4.1.3 Moving Data: Memory and the System Buses

A processor cannot work in isolation. It must request instructions and data from memory, send results back, and exchange information with input and output controllers. This page explains how those transfers are coordinated through the system bus.

By the end of this section, you should be able to:

Explain how the Immediate Access Store supports processor activity.
Describe a bus as a pathway for transferring binary signals.
Distinguish the address, data and control buses by purpose and direction.
Explain how the MAR, MDR and Control Unit take part in memory transfers.
Trace original memory-read, memory-write and input-read transactions.

Memory Available to the Processor

The processor needs rapid access to the instructions and working data used by a running program. The memory that the CPU can address directly is called the Immediate Access Store (IAS). In the syllabus model, this includes the memory locations from which the processor can directly request content.

Immediate Access Store (IAS): memory that can be addressed directly by the processor while programs are running.

A location in memory has an address and some stored content. The address identifies the location; the content is the binary instruction or data held there.

Memory address	Example content	Possible interpretation
1845	`LDD 1846`	An instruction that requests the content of another location.
1846	`27`	A calibration value used by a program.
1847	`ADD #6`	An instruction that adds an immediate value.

Common mistake: An address and the content stored at that address are not the same thing. The number 1846 identifies a location; the value 27 is the content currently stored there.

What Is a Bus?

A bus is a collection of pathways used to carry binary signals between components. In a simplified parallel bus, several wires carry several bits at the same time. A bus is a transfer route rather than a storage area.

Bus: a set of communication pathways used to transfer addresses, data or control signals between computer components.

The CPU, memory and input/output controllers use the system bus to complete a transaction. Each transaction must communicate three different ideas:

Question	Meaning	Bus involved
Where?	Which memory location or I/O controller is involved?	Address bus
What?	Which instruction or data value is being transferred?	Data bus
Which action and when?	Is this a read or write, and when should components respond?	Control bus

The Three Parts of the System Bus

The term system bus describes three buses working together. They carry different kinds of signals and do not all use the same direction.

Bus	Purpose	Direction in the syllabus model	Closely associated CPU part
Address bus	Identifies the selected memory location or I/O controller.	One-way from the CPU.	Memory Address Register (MAR)
Data bus	Transfers the binary content involved in the operation.	Bidirectional.	Memory Data Register (MDR)
Control bus	Carries commands, timing information and status signals.	Signals travel in both directions overall.	Control Unit (CU)

The address bus

Before a memory or I/O operation can happen, the CPU must identify the destination or source. The selected address is held in the MAR and placed on the address bus. In this model, addresses travel away from the CPU.

The data bus

The data bus carries the binary content being transferred. During a read, content moves towards the CPU. During a write, content moves away from it. An instruction, a numerical value, a character code or even an address treated as data may travel on this bus.

The control bus

The control bus coordinates the transaction. For example, the Control Unit may issue a memory read or memory write signal. Other control lines can carry timing, readiness or interrupt information back towards the processor.

Exam tip: A strong comparison states both what a bus carries and which direction its signals travel. Avoid vague statements such as “it connects the CPU to memory”.

Worked Process: Reading from Memory

Imagine that a climate-control program needs the calibration value stored at address 1846. That location currently contains 27.

Stage	Action	Main hardware involved
1	The CPU places `1846` in the MAR.	CPU and MAR
2	The MAR sends `1846` along the address bus.	MAR and address bus
3	The Control Unit sends a memory-read signal.	CU and control bus
4	Memory places `27` on the data bus.	Memory and data bus
5	The MDR receives and temporarily holds `27`.	MDR

Memory read: a transaction in which content is copied from a selected memory location towards the processor. Reading does not normally remove the original content from memory.

Worked Process: Writing to Memory

Suppose the processor has calculated a new result, 73, which must be stored at address 2190.

Stage	Action	Main hardware involved
1	The CPU places `2190` in the MAR.	CPU and MAR
2	The value `73` is placed in the MDR.	CPU and MDR
3	The address bus identifies location `2190`.	MAR and address bus
4	The data bus carries `73` towards memory.	MDR and data bus
5	The Control Unit sends a memory-write signal, so memory stores the value.	CU, control bus and memory

Common mistake: Do not reverse MAR and MDR. The MAR holds where the transfer is aimed; the MDR holds what is being transferred.

Transfers Involving Input and Output

The same three-bus pattern can be used when the processor communicates with an I/O controller. The address bus selects the controller, the control bus specifies the required operation, and the data bus carries the content.

For example, an input controller might report the character code 75. The CPU selects that controller, issues an input-read signal, and receives the code through the data bus into the MDR.

Exam tip: Refer to an I/O controller or interface rather than implying that every peripheral is wired directly to the processor.

Interactive: System Bus Transfer Simulator

Choose an operation and move through it one stage at a time. The simulator highlights the active bus and shows how the MAR, MDR and Control Unit contribute.

CPU MAR · MDR · CU

Address bus

Data bus

Control bus

Memory Addresses and stored content

I/O controller Interface to a peripheral

Address bus Waiting

Data bus Waiting

Control bus Waiting

Step 1 of 5

Prepare the transfer

Select an operation or click Next step to begin.

Common Mistakes and Misconceptions

A bus transfers signals; it does not permanently store them.
The address bus identifies a location. It does not carry the content stored there.
The data bus is bidirectional because reads and writes move content in opposite directions.
The control bus carries commands and status information, not ordinary program data.
The MAR stores an address, while the MDR temporarily holds transferred content.
A memory read copies content; it does not normally erase the memory location.

Practice

Core questions

Explain the difference between a memory address and memory content.
State the purpose and direction of each part of the system bus.
Explain why the data bus must be bidirectional.
Describe the roles of the MAR and MDR during a memory read.
Describe a complete memory-write transaction for value 46 and address 3072.
Correct this statement: “The MDR sends the target location along the address bus.”

Apply your understanding

A processor must read the instruction stored at address 5124. Write five ordered steps showing how the CPU, MAR, address bus, control bus, data bus, memory and MDR are involved.

Answer structure: For a transfer question, write the sequence in the order address → control signal → content transfer → destination register or memory location.

Review

Concept	Essential idea
IAS	Memory that the processor can address directly.
Address bus	Carries the selected address away from the CPU; linked to the MAR.
Data bus	Carries transferred binary content in either direction; linked to the MDR.
Control bus	Carries commands, timing and status signals; coordinated by the CU.
Memory read	Copies content from a selected location towards the processor.
Memory write	Stores transferred content at a selected memory location.

Final check: Can you identify where, what and which operation in any memory transaction? Those three ideas map directly to the address, data and control buses.