A-Level Computer Science / Unit 4: CPU Operation and Low-Level Processing

4.1.6 The Fetch–Decode–Execute Cycle

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4.1.6 The Fetch–Decode–Execute Cycle

A stored program is useful only if the processor can repeatedly obtain its instructions, interpret them and carry out their effects. The fetch–decode–execute cycle coordinates those actions using registers, buses, memory and the Control Unit.

By the end of this section, you should be able to:

  • Describe the fetch, decode and execute stages in the correct order.
  • Explain the roles of the PC, MAR, MDR and CIR during instruction fetching.
  • Connect each external transfer to the address, data and control buses.
  • Read and write register transfer notation for the fetch stage.
  • Explain why the PC normally advances and why a jump can replace that value.
  • Trace an original instruction through one complete processor cycle.

The Cycle as a Repeating Process

The processor works on one current instruction at a time in the simplified model used here. When one instruction has been completed, the next cycle can begin.

1. Fetch Bring the next instruction from memory into the CPU.
2. Decode Interpret the opcode and determine what resources are needed.
3. Execute Carry out the operation and store any result.
Fetch–decode–execute cycle: the repeated sequence through which a processor obtains, interprets and carries out program instructions.

Registers and Buses Used in the Fetch

The fetch stage combines internal register transfers with an external memory-read transaction.

Component Role in the fetch stage Information held or carried
Program Counter (PC) Identifies the instruction that should be fetched next. A memory address
Memory Address Register (MAR) Holds the address currently being sent to memory. A memory address
Memory Data Register (MDR) Receives the instruction returned by memory. The fetched instruction
Current Instruction Register (CIR) Holds the instruction while it is decoded and executed. The current instruction
Address bus Carries the selected address from the CPU to memory. The address copied from the MAR
Data bus Carries the instruction from memory towards the CPU. The binary instruction
Control bus Carries the memory-read command and timing signals. Control signals

The Fetch Stage

Consider an original example in which the PC initially stores address 730. Memory location 730 contains a binary instruction whose human-readable interpretation is ADD #11.

Memory address Illustrative stored binary Human-readable interpretation
730 0011 0000 1011 ADD #11
731 0101 0011 0000 STORE 816
732 1001 0010 1110 JUMP 750

The binary encodings above are illustrative and are not intended to define a real processor's instruction set.

Stage 1: prepare the address

The content of the PC is copied into the MAR. Both registers now contain 730. This is an internal CPU transfer.

MAR ← [PC]

Stage 2: request the instruction

The MAR places 730 on the address bus. The Control Unit sends a memory-read signal through the control bus, telling memory to return the content of the selected location.

Stage 3: receive the instruction and advance the PC

Memory sends the binary instruction along the data bus into the MDR. During this part of the fetch, the PC is also incremented so that it contains 731, the address of the following instruction.

MDR ← [[MAR]]   ;   PC ← [PC] + 1

Stage 4: make it the current instruction

The instruction is copied from the MDR into the CIR. The fetch is now complete and the instruction is ready to be decoded.

CIR ← [MDR]
Common misconception: Incrementing the PC does not alter the instruction in the CIR. It prepares the address for a possible next sequential fetch.

Register Transfer Notation

Register transfer notation records where information comes from and where it goes. The destination appears on the left of the arrow; the source appears on the right.

Register transfer notation: a compact notation used to describe transfers and simple operations involving register contents and memory.
Notation How to interpret it
MAR ← [PC] Copy the content of the PC into the MAR.
PC ← [PC] + 1 Add 1 to the content of the PC and store the result back in the PC.
MDR ← [[MAR]] Use the address held in the MAR, then copy the content of that memory location into the MDR.
CIR ← [MDR] Copy the fetched instruction from the MDR into the CIR.
; The separated operations can occur during the same stage or clock interval in this model.
Common mistake: [MAR] means the address stored in the MAR. [[MAR]] means the content found in memory at that address.
Exam tip: Use the word copy rather than move when the source keeps its original content.

The Decode Stage

The Control Unit examines the binary instruction held in the CIR. It separates the operation code from any operand information and determines what action the instruction represents.

Instruction field Purpose Example from the current instruction
Opcode Identifies the operation to perform. Add
Operand Provides a value, register or address needed by the operation. Immediate value 11

The Control Unit then produces the control signals needed for execution. It may select registers, activate the ALU or arrange another memory transfer.

Common misconception: Decode does not perform the calculation. It determines which operation must happen and how the processor should carry it out.

The Execute Stage

The execute stage depends on the decoded instruction. There is no single action that represents every execution.

Instruction category Possible execution activity Component commonly involved
Arithmetic or logic Perform a calculation or comparison and update a result or status flags. ALU, ACC and Status Register
Data movement Copy content between registers, memory or an I/O controller. Registers, buses and Control Unit
Program control Replace the PC with a target address when a jump is taken. Control Unit and PC

In the example instruction ADD #11, suppose the ACC initially contains 24. The ALU adds 11, and the new ACC value becomes 35.

ACC before: 24 Immediate operand: 11 ACC after: 35

Sequential Flow and Jump Instructions

Incrementing the PC assumes that execution will continue at the next sequential address. That is the normal case, but it is not guaranteed.

If the decoded instruction is a jump and its condition is satisfied, execution replaces the incremented PC value with the jump target. For example, after fetching an instruction from address 732, the PC might temporarily contain 733 and then be changed to 750 when the jump is executed.

Common mistake: Do not state that the PC always contains the current instruction's address. During and after the fetch, it normally points to the next sequential instruction unless execution changes it.

What Happens at the Cycle Boundary?

Once the instruction has completed, the processor reaches a safe boundary before the next fetch begins. In the simplified model, this is where pending interrupts can be considered.

The causes, priorities and handling of interrupts—including the Interrupt Service Routine—are covered fully in 4.1.7 Interrupts and Interrupt Service Routines.

Cycle boundary: the point after the current instruction has completed and before normal execution continues with the next fetch.

Interactive: Fetch–Decode–Execute Visualiser

Step through the instruction stored at address 730. Watch the registers, buses, Control Unit and ALU change as the instruction moves through the cycle.

PC 730 Next instruction address
MAR — Address currently selected
MDR — Content returned by memory
CIR — Instruction being decoded/executed
ACC 24 Current calculation value
Control Unit Waiting
ALU Idle
Address bus Idle
Data bus Idle
Control bus Idle

Memory

730 0011 0000 1011 ADD #11
731 0101 0011 0000 STORE 816
732 1001 0010 1110 JUMP 750
1. PC → MAR
2. Address + READ signal
3. Memory → MDR and PC + 1
4. MDR → CIR
5. Decode
6. Execute

Step 1 of 6

Copy the next address into the MAR

The PC contains 730. Its content is copied into the MAR so the processor can select the correct memory location.

MAR ← [PC]

Common Mistakes and Misconceptions

  • The PC contains the address of the next instruction, not the instruction itself.
  • The MAR holds an address; the MDR can hold the instruction returned from memory.
  • The address bus carries the address, while the data bus carries the instruction.
  • The decode stage interprets the instruction but does not itself perform the operation.
  • The ALU is used only when the instruction requires arithmetic or logical processing.
  • The PC is normally incremented during the fetch, but a later jump may overwrite it.
  • [MAR] and [[MAR]] have different meanings.

Exam Tips

Building a precise fetch-stage answer

  1. State that the PC address is copied to the MAR.
  2. Explain that the address goes to memory and a read signal is issued.
  3. State that the instruction returns to the MDR through the data bus.
  4. Mention that the PC is incremented.
  5. Finish by copying the instruction from the MDR to the CIR.
For register transfer notation: explain every symbol in words. Do not merely rewrite the notation.

Practice

Core questions

  1. Describe the fetch stage using the PC, MAR, MDR and CIR.
  2. Explain how all three parts of the system bus contribute to fetching an instruction.
  3. Interpret MDR ← [[MAR]] in a complete sentence.
  4. Write register transfer notation for incrementing the PC.
  5. Explain the role of the Control Unit during decoding.
  6. Explain why the ALU is not necessarily used for every instruction.
  7. Explain why a jump instruction may replace the incremented PC value.

Trace challenge

The PC initially contains 912. Memory location 912 contains an instruction. State the contents of the PC, MAR, MDR and CIR immediately after the fetch stage, assuming that the PC advances by one.

Correct the explanation

A student writes: “The PC sends the instruction to the MAR. The MAR then sends the instruction to memory, where it is executed.” Rewrite this explanation accurately.

Review

Stage Essential event Key hardware
Fetch The next instruction is read from memory into the CIR through the MAR and MDR. PC, MAR, MDR, CIR and system buses
Decode The opcode and operand are interpreted and control signals are prepared. CIR and Control Unit
Execute The required operation is performed and any result is stored. Depends on the instruction
Cycle boundary The processor is ready to continue or respond to a pending interrupt. Control Unit and relevant registers
Final check: Can you describe both the logical stages and the physical transfers among registers, buses and memory?