A-Level Computer Science / Unit 4: CPU Operation and Low-Level Processing

4.2.4 Understanding the Assembly Instruction Set

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4.2.4 Understanding the Assembly Instruction Set

An instruction set is the collection of operations available to a processor. This page organises the required assembly instructions by purpose and focuses on what each instruction changes: a register, a memory location, the comparison flag, the program counter, an input/output device, or the running state of the program.

By the end of this section, you should be able to:

  • Classify instructions as data movement, input/output, arithmetic, compare, or control flow.
  • Interpret every instruction in the required teaching instruction set.
  • Identify the source and destination of data for a given instruction.
  • Distinguish direct, indirect, indexed and immediate instruction forms.
  • Explain how comparison instructions work with conditional jumps.
  • Predict which parts of processor state change after one instruction.
  • Use absolute or symbolic addresses and denary, binary or hexadecimal literals correctly.

What Belongs on This Page?

This page covers the instruction groups required in 4.2 Assembly Language: data movement, input/output, arithmetic, comparison, and unconditional or conditional control flow.

Content Location in the new structure
Meaning and effect of individual instructions 4.2.4 Understanding the Assembly Instruction Set
Following a complete program line by line 4.2.5 Tracing Assembly Programs
AND, OR, XOR, LSL and LSR 4.3 Bit Shifts, Masks and Device Control
Important structural change: The old page included shifts and bitwise logic. In the current syllabus, those operations belong to the separate 4.3 Bit Manipulation section, so they are not duplicated here.

How to Read an Assembly Instruction

Begin with the mnemonic, then inspect the operand. A strong explanation identifies the source of the value, the destination, and the addressing rule.

1. Read the mnemonic LDD Which operation will occur?
2. Interpret the operand VALUE Value, address, symbol or register?
3. State the effect memory[VALUE] → ACC What changes?
Notation Meaning Example
<address> An absolute number or a symbolic label. 640 or COUNT
<register> The register named in the instruction. ACC or IX
#n An immediate denary value. #14
Bn An immediate binary value. B00001110
&n An immediate hexadecimal value. &0E
Instruction set: the complete collection of machine operations and corresponding assembly mnemonics supported by a processor.

Shared Processor State for the Worked Examples

The examples below are independent. Before each example, reset the fictional processor to this state:

ACC18
IX3
PC710
Equal flag0
Input characterK
Memory address Stored content Possible use
64027Ordinary data
641645Pointer to address 645
64212Arithmetic operand
64388Indexed target when IX = 3
64419Comparison value
64554Indirect target
6460Empty storage location

Data Movement Instructions

These instructions copy data between literals, memory, ACC and IX. They do not all use the operand in the same way.

Instruction form Effect Example using the shared state
LDM #n Copy immediate value n into ACC. LDM #23 makes ACC = 23.
LDR #n Copy immediate value n into IX. LDR #5 makes IX = 5.
LDD <address> Copy the content at the direct address into ACC. LDD 644 makes ACC = 19.
LDI <address> Follow the pointer stored at the given address, then load into ACC. LDI 641: 641 → 645 → 54, so ACC = 54.
LDX <address> Add IX to the address, then load the content at the calculated address into ACC. LDX 640: 640 + 3 = 643, so ACC = 88.
MOV <register> Copy ACC into the named register. MOV IX makes IX = 18.
STO <address> Copy ACC into the given memory location. STO 646 makes memory[646] = 18.
Common mistake: A load instruction changes a register. A store instruction changes memory. STO 646 does not load 646 into ACC.

Input and Output Instructions

Instruction Effect What changes?
IN Read one keyboard character and place its character code in ACC. If the input is K, ACC becomes 75 in ASCII.
OUT Display the character represented by the code in ACC. If ACC contains 66, the output character is B.
Opcode-only instruction: an instruction that needs no explicit operand. In this teaching set, IN, OUT and END are written without operands.
Common misconception: OUT does not display the denary number written in ACC. It treats the value as a character code.

Arithmetic Instructions

Arithmetic instructions update ACC or the explicitly named register. Always check whether the operand is an immediate value or a memory address.

Instruction form Effect Example
ADD <address> ACC ← ACC + memory[address] ADD 642: 18 + 12 = 30.
ADD #n / Bn / &n ACC ← ACC + immediate value ADD #7, ADD B00000111 and ADD &07 all make ACC = 25.
SUB <address> ACC ← ACC − memory[address] SUB 642: 18 − 12 = 6.
SUB #n / Bn / &n ACC ← ACC − immediate value SUB #5 makes ACC = 13.
INC <register> Add 1 to ACC or IX. INC ACC makes ACC = 19.
DEC <register> Subtract 1 from ACC or IX. DEC IX makes IX = 2.
Exam tip: Do not write “add the address”. For ADD 642, the processor adds the content stored at address 642.

Compare Instructions

In this teaching instruction set, comparison checks for equality. The instruction does not replace ACC. Instead, it updates an equality result in the Status Register.

Instruction form Value compared with ACC Example result
CMP <address> The content stored at the direct address. CMP 644: 18 ≠ 19, so Equal flag = 0.
CMP #n The immediate denary value. CMP #18: 18 = 18, so Equal flag = 1.
CMI <address> The value found using indirect addressing. CMI 641: pointer 645 → value 54; 18 ≠ 54, so flag = 0.
Common misconception: A comparison does not jump and does not normally alter ACC. It records a result for a later conditional jump to inspect.

Unconditional Jumps, Conditional Jumps and END

Jump instructions affect control flow by changing the Program Counter. Conditional jumps depend on the result of a previous comparison.

Instruction form Condition Effect
JMP <address> Always PC becomes the target address.
JPE <address> Jump when the previous comparison was true. If Equal flag = 1, PC becomes the target.
JPN <address> Jump when the previous comparison was false. If Equal flag = 0, PC becomes the target.
END No condition Stop the program and return control to the operating system. 
CMP #18
JPE MATCH
JMP DIFFERENT

The compare sets the flag. JPE reads that flag. If the equality test succeeded, the target labelled MATCH is loaded into PC; otherwise execution continues to the next instruction.

Strong explanation: “JPE checks the equality result set by a previous compare instruction; when true, the target address replaces the next sequential value in PC.”

Interactive: Instruction Effect Explorer

Choose an instruction group, select an instruction, then animate one execution. The explorer resets the processor before each example so that the effect of a single instruction remains clear.

Data movement

Move a value between a literal, memory, ACC and IX.

ACC 18
IX 3
Equal flag 0
PC 710
Input K
Output —
Program state Running

LDM #23

Immediate load

The value 23 is copied directly into ACC.

Immediate value 23 → ACC

Common Mistakes and Misconceptions

  • LDM loads ACC, while LDR loads IX.
  • MOV IX copies ACC into IX; it does not copy IX into ACC.
  • LDD, LDI and LDX all load ACC but find the value differently.
  • STO changes memory, not ACC.
  • IN and OUT use character codes.
  • CMP and CMI set a comparison result; they do not jump.
  • JPE and JPN read a previous comparison result; they do not perform a new comparison.
  • END is not a jump to address zero; it returns control to the operating system.
  • AND, OR, XOR, LSL and LSR belong to 4.3 and are intentionally not included here.

Exam Tips

Use a source → destination sentence

Example: “LDD VALUE copies the content stored at the address represented by VALUE into ACC.”

Name the addressing behaviour

For LDI, state both memory lookups. For LDX, show address + IX.

Keep compare and jump separate

A compare instruction sets a result. A conditional jump checks that result and may update PC.

Practice

Classify and explain

For each instruction, state its group, source, destination and final effect:

  1. LDR #6
  2. LDI POINTER
  3. STO RESULT
  4. ADD B00001011
  5. CMI TARGET
  6. JPN RETRY
  7. OUT

Independent state challenge

Before each instruction, assume ACC = 31, IX = 4, Equal flag = 0, and:

AddressContent
82017
821824
8229
82342
82431
8250

Find the changed state after each independent instruction: LDD 823, LDI 821, LDX 820, SUB #6, CMP 824, and STO 825.

Control-flow reasoning

CMP #31
JPN NOT_EQUAL
JPE EQUAL

Starting with ACC = 31, state the flag result and explain which conditional jump changes PC.

Review

Instruction group Main question to ask Key mnemonics
Data movement Where is the value copied from and to? LDM, LDR, LDD, LDI, LDX, MOV, STO
Input/output How does a character code enter or leave ACC? IN, OUT
Arithmetic Is the operand a memory value or an immediate value? ADD, SUB, INC, DEC
Compare What value is compared with ACC, and what flag result is set? CMP, CMI
Control flow Does PC change, and under what condition? JMP, JPE, JPN, END
Final check: Can you explain each instruction by naming the source, destination, addressing rule and changed processor state?